Embodiments of the present invention relate to electro-static discharge (ESD) protection circuits that prevent internal circuits in a semiconductor integrated circuit from being damaged by an overvoltage under ESD events applied to a power supply node in the semiconductor integrated circuit.
FIG. 6 is a block diagram illustrating an example configuration of prior art ESD protection circuits. The ESD protection circuit 30 shown in FIG. 6 is an active clamp-type power supply ESD protection circuit described in FIG. 1 of JP 2012-253241 A (hereinafter referred to as Patent Document 1), and is formed of an overvoltage detection circuit 12 and a clamp circuit 14.
The overvoltage detection circuit 12 is provided to detect an overvoltage (e.g. 3 V) under ESD events to the power supply node, which is higher than a power supply voltage VDD (e.g. 1.1 V) under normal operation, and to output a detection signal. The overvoltage detection circuit 12 is formed of an RC time constant circuit 20 having a resistive element R and a capacitive element C, and an inverter 22 having a PMOS (P-type MOS transistor) MP1 and an NMOS (N-type MOS transistor) MN1.
The resistive element R and the capacitive element C of the RC time constant circuit 20 are serially connected between the power supply node and a ground node to which a ground voltage VSS is supplied under normal operation.
The PMOS MP1 and the NMOS MN1 of the inverter 22 are serially connected between the power supply node and the ground node, and have their gates to which an output signal n1 of the RC time constant circuit 20 is inputted. The output signal n1 is outputted by an internal node n1 located between the resistive element R and the capacitive element C. The inverter 22 inversely-outputs the output signal n1 of the RC time constant circuit 20, as the detection signal described above.
In response to the detection signal, when an overvoltage to the power supply node is detected, the clamp circuit 14 connects the power supply node to the ground node to allow a large current due to the overvoltage applied to the power supply node to flow to the ground node, to clamp the voltage of the power supply node so as to protect internal circuits of a semiconductor integrated circuit operating on the power supply voltage VDD. The clamp circuit 14 is formed of an NMOS MN0.
The NMOS MN0 is connected between the power supply node and the ground node, and has its gate to which an output signal of the inverter 22, i.e., a detection signal n0, is inputted. The detection signal n0 is outputted from an internal node n0 located between the PMOS MP1 and the NMOS MN1.
Next, operation of the ESD protection circuit 30 will be described.
Under normal operation, when a power supply voltage VDD is supplied to the power supply node, the capacitive element C is charged to the power supply voltage VDD. Accordingly, the output signal n1 of the RC time constant circuit 20 keeps high level (H). The PMOS MP1 is in OFF state, and the NMOS MN1 is in ON state. Then the detection signal n0 keeps low level (L), and the NMOS MN0 is in OFF state. Thus, the ESD protection circuit 30 under the normal operation has no effect to the internal circuits operating on the power supply voltage VDD.
Under ESD events, when an overvoltage is applied to the power supply node, the power supply node rises steeply, while the output signal n1 of the RC time constant circuit 20 rises slower than the power supply node, due to the behavior of the RC time constant circuit 20. Accordingly, the output signal n1 of the RC time constant circuit 20 becomes L for a period until the capacitive element C is charged by the overvoltage through the resistive element R, that is, for a period of the time constant RC supplied from the RC time constant circuit 20. The detection signal n0 becomes H, for a period corresponding to the time constant RC, and then the NMOS MN0 is turned ON.
Thus, under ESD events, a large current due to the overvoltage applied to the power supply node is allowed to flow to the ground node through the NMOS MN0, so that the voltage of the power supply node is clamped to protect the internal circuits operating on the power supply voltage VDD.
As described above, the prior art ESD protection circuit 30 of active clamp-type power supply is designed such that the activation of the ESD protection circuit 30 is to be triggered by the RC time constant circuit 20 based on the assumption of steep rising of the overvoltage applied to the power supply node under ESD events. However, even when such steep rising of the power supply voltage VDD is caused as a result of applied voltage to the power supply node at Power-On, the prior art ESD protection circuit 30 can operate as if it is under ESD events, allowing the large current flow from the power supply node to the ground node through the NMOS MN0.
Next, simulation results performed on the prior art ESD protection circuit 30 at Power-On will be described.
In this simulation, as shown in the upper left part in FIG. 7, three different predetermined voltages: a power supply voltage VDD under normal operation, i.e., 1.1 V; a voltage between the power supply voltage VDD under normal operation and the overvoltage under ESD events, i.e., 2 V; and an example overvoltage to be applied to the power supply node under ESD events, i.e., 3 V; are supplied to the power supply node with a rising time of 1 ns (the voltage of the power supply node is raised to each predetermined voltage in 1 ns), and each current that flows through the NMOS MN0 as indicated by the arrow in the right part in FIG. 7 is measured.
FIG. 8 is a graph showing simulation results of the ESD protection circuit at Power-On shown in FIG. 6. In this graph, the vertical axis represents current (A), and the horizontal axis represents time period (μs).
As shown in the graph, when a power supply voltage VDD under normal operation, i.e., 1.1 V is supplied to the power supply node in a rising time of 1 ns (VDD=1.1 V (1.1 V/ns)), a current flows through the NMOS MN0. Thus in this case, it can be seen that the NMOS MN0 is turned ON, immediately after Power-On and kept to be in ON state for a period corresponding to a time constant RC of the RC time constant circuit 20.
The results also shows that when 2 V which represents the voltage between the power supply voltage VDD under normal operation and the overvoltage under ESD events is supplied to the power supply node in a rising time of 1 ns (VDD=2 V (2 V/ns)), as well as when the example overvoltage 3 V is applied to the power supply node under ESD events in a rising time of 1 ns (VDD=3 V (3 V/ns)), the NMOS MN0 is turned ON for a period corresponding to the time constant RC of the RC time constant circuit 20, in either case.
From the above simulation results, it can be seen that the prior art ESD protection circuit 30 can act in a similar way as it is under ESD events, even when the power supply voltage VDD under normal operation is supplied to the power supply node in a steeply.
It can also be seen from the graph in FIG. 8, that when the rising of the power supply voltage VDD is steep, even 1.1 V of the power supply voltage VDD under normal operation can cause a current about 600 mA to flow for a period of 1 μs order. In an actual semiconductor integrated circuit, a plurality of the ESD protection circuits 30 shown in FIG. 6, may be laid out. For example, if a semiconductor integrated circuit has ten ESD protection circuits 30, a current about 6 A will flow for a time period of 1 μs order.
Therefore, for example, when the power supply voltage VDD rises steeply at Power-On, as in a hot-pluggable device, the ESD protection circuit 30 laid out on the device may malfunction at Power-On, which causes an excessively large current relative to the driving capacity of the power supply to flow. In that case, the device may not be allowed to start normally, and in a worst case, the power supply may oscillate.
In addition to the Patent Document 1 previously described, there are several related prior art documents, including, JP 2010-50312 A (hereinafter referred to as Patent Document 2) and JP 2012-195778 A (hereinafter referred to as Patent Document 3).
Patent Document 2 relates to ESD protection circuits that prevent internal circuits in a semiconductor integrated circuit from electrostatic discharging.
Patent Document 2 describes an ESD protection circuit which detects a voltage difference between a power supply and a ground to output it as a first detection signal so that the power supply and the ground are electrically connected once the first detection signal reaches a first threshold voltage between the power supply voltage under normal operation and the ground. The ESD protection circuit determines whether the voltage difference between the first detection signal and the ground reaches a second threshold voltage which is higher than the power supply voltage under normal operation, to output it as a second detection signal. Once the second detection signal reaches the second threshold voltage, the level of the first detection signal is controlled.
Patent Document 3 relates to ESD protection circuits for preventing internal circuits from being damaged by ESD.
In Patent Document 3, an ESD protection circuit is described, in which a first ESD pulse detection signal is outputted for a first predetermined period from the start of ESD event to a power supply terminal. A second ESD pulse detection signal is outputted for a third predetermined period, after the first ESD pulse signal is outputted and when the ESD event to the power supply terminal is maintained for a second predetermined period. The first predetermined period is determined to be shorter than the rising time of the power supply. The second predetermined period is determined to be shorter than the first predetermined period and longer than the application period of a spike noise to the power supply terminal. The third predetermined period is determined to be longer than the application period of the ESD pulse to the power supply terminal. When neither of the first ESD pulse detection signal and the second ESD pulse detection signal is outputted, a gate of an ESD protection driver that discharges the ESD pulse applied to the power supply terminal to a GND terminal, is connected to the GND terminal. When at least one of the first ESD pulse detection signal and the second ESD pulse detection signal is outputted, the gate of the ESD protection driver is insulated from the GND terminal. When the second ESD pulse detection signal is outputted, the gate of the ESD protection driver is connected to the power supply terminal. When the second ESD pulse detection signal is not outputted, the gate of the ESD protection driver is insulated from the power supply terminal.